Data processing system with instruction addresses identifying one of a plurality of registers including the program counter

ABSTRACT

A data processing system processor unit including memory addressing circuits. Operand addresses for identifying data storage locations comprise operand address mode and register selection bits. One of a plurality of registers in the processor unit, which includes the program counter, is selected by decoding the register selection bits. The selected register contents are transferred to the processor unit as data, data addresses or addresses of intermediate storage locations containing data addresses to provide direct, indirect or double deferred addressing. Data or data addresses interleaved with or obtained from information interleaved with instructions are obtained by selecting the program counter. This provides immediate, absolute, relative and deferred relative addressing. The selected register contents are modified if certain address modes are used. A given operation code can be combined with one or two operand addresses in order that each instruction can obtain data from locations in the most efficient manner.

United States Patent [72} inventors Harold L. McFarland, Jr.

Concord; James F. OLoughlin, Westford, both of Mass. [21] Appl. No. 21,973 [22] Filed Mar. 23, 1970 [45] Patented Oct. 19, 1971 [73] Assignee Digital Equipment Corporation Maynard, Mass.

[54] DATA PROCESSING SYSTEM WITH INSTRUCTION ADDRESSES IDENTIFYING ONE OF A PLURALITY 0F REGISTERS INCLUDING THE PROGRAM COUNTER 24 Claims, 24 Drawing Figs.

[52] US. Cl 340/1725 [51] Int. Cl G06f 9/20 [50] Field of Search 340/1725 {56] References Cited UNITED STATES PATENTS 3,425,039 1/1969 Bahrs et a1. 340/1725 3,461,433 8/1969 Emerson 340/1725 3,015,441 1/1962 Rent et a1. 340/172.5X

Primary Examiner-Gareth D. Shaw Assistant Examiner-Sydney R. Chirlin Attorney-Cesari and McKenna ABSTRACT: A data processing system processor unit including memory addressing circuits. Operand addresses for identifying data storage locations comprise operand address mode and register selection bits. One ofa plurality of registers in the processor unit, which includes the program counter, is selected by decoding the register selection bits. The selected register contents are transferred to the processor unit as data, data addresses or addresses of intermediate storage locations containing data addresses to provide direct, indirect or double deferred addressing. Data or data addresses interleaved with or obtained from information interleaved with instructions are obtained by selecting the program counter. This provides immediate, absolute, relative and deferred relative addressing. The selected register contents are modified if certain address modes are used. A given operation code can be combined with one or two operand addresses in order that each instruction can obtain data from locations in the most efiicient manner.

OPERAND ADDRESS 5 l 4 l s 2 l l i In ADDRESS REGISTER L MODE SELECTION ADDRESS ADDRESS REGISTER SELECTED Mo E BUS DEFINITION MODE 5 4 13 MW SE ECTIOh BITS REGISTER Q 0 Q 9 REGISTER-DIRECT a o 0 R0 L REGISTER I a a I DEFERRED o o l RI r AUTO-INC 2 9 I DIRECT 9 0 R2 AUTO-INC 3 o l I DEFERRED a I I R3 AUTODEC l 4 DIRECT 9 9 R4 AUTO-DEC 5 l 9 DEFERRED 9 R5 INDEX .1 e I I a D'RECT L l l 0 R6 INDEX 7 L I I DEFERRED Ll I I R7 PATENTEUncr ISISII $614,741

sum D10F21 CONTROL CONTROL CONTROL FFEI'Q". FFFT'Q PERPI'ERAL PERIPIERAL ME WY LNT N UNT I up? K OPERAND ADDRESS x 5 I 4 I 3 2 1 I 1 a ADDRESS REGISTER MODE SELECTION ADDRESS ADDRESS DEFIMT'ON SELREECQIIEIEBRTS SELECTED MODE 3 2 l I REGISTER 0 Q Q Q REGISTER-DIRECT D G 0 RD REGISTER AUTO-INC 2 0 0 DIRECT 0 I 0 R2 AUTO-INC 3 O I I DEFERRED U I I R3 AUTO-DEC A T 5 I I?! I E I Q I R5 INDEX 6 l I 0 DIRECT I I 0 R6 INDEX 7 I I I DEFERRED I I R7 INVENTORS Y HAROLD L McFARLAND 4 JAMES F O'LOUGHLIN ATTORN E YS PAIENIEDUIII I9 IHII ISR O ISR'I ISR I SIIEEI U I [1F 21 UNIT 46.

TRANSFER THE INCREMENTED OUTPUT FROM THE ADDER UNIT 46 TO THE PC REGISTER;

TRANSFER THE INSTRUCTION FROM LOCATION DESIGNATED BY THE BUS ADDRESS REGISTER 34.

L DOES THE INSTRUCTION DEcDDE INSTRUCTION DEC ODER 64.

D EEDIJ ETHE I NSTRUCTION IN THE I AS A "HALT" INSTRUCTION? MAY THE INSTRUCTION BE EXECUTED YES IMMEDIATELY DOES THE INSTRUCTION HAVE TWO OPERAND ADDRESSES WITH THE NO IRST HAVING A NON-ZERO ADDRESS M009 YES usE THE FIRST OPERAND ADDREss As A DESIGNATED ADDRESS USE THE SINGLE OPERAND 0R sEcoND OPERAND ADDRESS As A DESIGNATED ADDRESS TRANSFER THE ADDER UNIT OUTPUT THE CONTENTS OF THE LOCATION ADDRESSED BY THE BUS ADDRESS REGISTER 34 TO THE B INPUT CIRCUIT 52.

TO THE SELECTED REGISTER; TRANSFER- FIG. 5A

HAROLD INVENTORS MGFARLAND BYJAMES F O'LOUGHLIN ATTORNEYS PATENTEDIICI I 9 ISTI SHEET USIIF 21 IND B DOES THE FIRST OPERAND Y P ADDRESS HAvE A MODE -I, vv i -2, 0R -4 OPERAND ADDRESS? BSR-I IF ADDRESS MODE -6 0R -7, TRANSFER DESIGNATED REGISTER CONTENTS TO THE A INPUT cIRcuIT 48aADD INDEX VALUE IN THE B INPUT cIRcuIT 52- IF OTHER'MODE,

NO DPERATID TRANSFER THE ADDER UNIT OUTPUT TO THE BUS ADDRESS REGISTER 34. TRANSFER THE CONTENTS OF THE LOCATION ADDRESSED BY THE BUS ADDRESS REGISTER 34 TO THE B INPUT CIRCUIT 52 DOES THE FIRST OPERAND ADDRESS HAVE A MODE '3 "5, OR '6 OPERAND ADDRESS 7 BSR-3 NO DPERATIDNT TRANSFER THE ADDER UNIT OUTPUT To THE BUS ADDRESS REGISTER 34.

TRANSFER THE CONTENTS OF THE LOCATION ADDRESSED BY THE BUS ADDRESS REGISTER 34 TO THE B INPUT CIRCUIT 52 )LES,

YES

I NO IS THE OPERAND ADDRESS THE FIRST OF TWO IN THE INSTRUCTION? UNIT 46 IN THE SOURCE REGISTER sToRE THE OUTPUT FROM THE ADDE'R IN THE REGISTER MEMORY 40 FIG. 5B

INVENTORS HAROLD Lv McFARLAND JAMES F O'LOUGHLIN BY PAIENTEDUEI I 9 IBII 3, 614, 741

SHEET USIIF 21 A V A ,7 ISHTHE'JNSTRUCTION DECODED As v55 A JMP TRANSFER INSTRUCTION? ISR BY THE INSTRUCTION OPERAND TIQTAKISFEAFHE ADDRESS DEFINED ADDRESS TO THE PC REGISTER ISHTHEHINSTRUCTION 0500050 As A N JSR TRANSFER INSTRUCTION YES TRANSFER THE ADDRESS DEFINED BY ISR-Q THE INSTRUCTION OPERAND ADDRESS TO THE TEMP REGISTER EXECUTE FIG. 5C

INVENTORS HAROL D L Mc FAR LAND YJAMES F O'LQUGHLIN PAIENTEDIIBT I9 IQTI lSR-O ISRI ISR-Z ISR- 3 ISR- 4 SHEET O'IUF 21 QIs THE INSTRUCTION DECODED AS N0 JSR INSTRUCTION TYES BSR-l BSR-Z BSR-3 BSR-G BSR-G BSR-7 TRANSFER THE PC REGISTER CONTENTS TO THE B INPUT CIRCUIT 52v TRANSFER THE CONTENTS OF THE ADDER UNIT 52 TO THE R5 REGISTER.

TRANSFER THE CONTENTS OF THE TEMP MEMORY 40 TO THE B INPUT CIRCUIT 52.

REGISTER IN THE REGISTER TRANSFER THE CONTENTS OF THE ADDER THE REGISTER MEMORY 40.

UNIT TO THE PC REGISTER IN IS THE INSTRUCTION DECODED AS A RTS INSTRUCTION FIG. 6A

INVENTORS HAROLD L. Mc FARLAND BYJAMES F. O'LOUGHLIN PATENTEDum 19 IBTI SHEET OBUF 21 ISR-4 TRANSFER THE R5 REGISTER CONTENTS TO THE B INPUT CIRCUIT 52.

ISR-S TRANSFER THE ADDER UNIT OUTPUT TO THE PC REGISTER IN THE REGISTER MEMORY 4O BSR-I ISR-G BSR-3 ISR-T TRANSFER THE ADDER UNIT OUTPUT TO THE R5 REGISTER IN THE REGISTER MEMORY 40.

IS THE INSTRUCTION DECODED AS A RTI INSTRUCTION YES ISR- 4 BSR-B TRANSFER THE CONTENTS OF THE SP REGISTER IN THE REGISTER MEMORY 40 TO THE 8 INPUT CIRCUIT 52.

TRANSFER THE ADDER UNIT OUTPUT TO THE BUS ADDRESS REGISTER 34;TRANS- FER AN INCREMENTING VALUE TO THE A INPUT CIRCUIT 48.

TRANSFER THE INCREMENTED VALUE FROM THE ADDER UNIT 46 TO THE SP REGISTER IN THE REGISTER MEMORY 40, TRANSFER THE CONTENTS OF THE LOCATION DEFINED BY THE BUS ADDRESS REGISTER 34 TO B INPUT CIRCUIT 52.

DEC

FIG. 6B

INVENTORS HAROLD 'L. McFARLAND BYJAMES O'LOUGHLIN AT TORN E YS PAIENIEDUEI I8 IsrI 3,6 1 4, 741

SHEEI us 0F 21 TRANSFER THE ADDER UNIT OUTPUT To THE PC REGISTER IN THE REGISTER MEMORY 4o.

BSR-l TRANSFER THE CONTENTS THE SP REG.

ISTER IN THE REGISTER MEMORY 40 TO THE B INPUT CIRCUIT 52.

BSR-2 TRANSFER THE ADDER UNIT OUTPUT TO THE BUS ADDRESS REGISTER 34;

TRANSFER AN INCREMENTING VALUE TO THE A INPUT CIRCUIT 48 BSR-3 TRANSFER THE INCREMENTED VALUE FROM THE ADDER UNIT 46 TO THE SP REG- ISTER IN THE REGISTER MEMORY 40; TRANSFER THE CONTENTS OF THE LOCATION DEFINED BY THE BUS ADDRESS REGISTER 34 TO THE B INPUT CIRCUIT 52.

ISR-6 TRANSFER THE ADDER UNIT OUTPUT TO THE STATUS REGISTER 59 IN THE PRIORITY CONTROL UNIT 58.

ISR

Em I I IS THE INSTRUCTION DECODED AS A )N() BRANCH INSTRUCTION 72 YES I TRANSFER THE CONTENTS OF THE PC REG- ISR-I IsTER IN THE REGISTER MEMORY 40 To THE A INPUT CIRCUIT48.

TRANSFER THE OUTPUT FROM THE ADDER lsR-g UNIT 46 TO THE PC REGISTER IN THE REGISTER MEMORY 40.

FIG. 6C

INVENTORS HAROLD L. McFARLAND JAMES F OLOUGHLIN NO IsR-I TRANSFER THE CONTENTS OF THE sOuRcE REGISTER IN THE REGISTER MEMORY 4-0T0 THE OTHER LATCH.

DOES THE INSTRUCTION REQUIRE THE )NO ADDITION OF CONSTANTS YES TRANsFER THE CONSTANT TO THE APPRO- PRIATE ONE OF INPUT CIRCUITS 48 OR 52.

Is THE INsTRucTION DECODED As A r19 BIT OR A BIC INsTRucTION YEs SW2 TRANsFER THE CONTENTS OF THETADOER UNIT 46 TO THE TEMP REGISTER IN THE REGISTER MEMORY 40.

. TRANsEER THE TEMP REGISTER cONTENTs lSR-3 IN THE REGISTER MEMORY 40 To THE A INPUT cIRcuIT 4e.

PATENTEDIIcI I 9 Ian 3,514,741

SHEET 100F21 OES THE SECOND OPERAND ADDRESS IN A TWO OPERAND ADDRESS IN- STRUCTION OR THE SINGLE OPERAND IN A SINGLE OPERAND ADDRESS YES I INSTRUCTION HAVE A ZERO ADDRESS MODE TRANSFER THE CONTENTS OF THE ISR Q LOCATION DEFINED BY THE OPERAND ADDRESS FROM THE SELECTED REG ISTER IN THE REGISTER MEMORY 4OTO ONE OF THE INPUT CIRCUITS 48 OR 52.

EMMA DOES THE INSTRUCTION HAVE TWO YES OPERAND ADDRES SES FIG. 60

INVENTORS HAROLD LI McFARLAND Y JAMES F O'LOUGHLIN PATENTEDIIcI 19 IS?! ALTER THE CONDITION CODES IN THE STATUS REGISTER 59 IN THE STATUS UNIT 58 |sR 4 N0 Is THE INSTRUCTION DECODED AS A TST, BIT, BIC, OR CMP INSTRUCTION? ISR-4 YES I Q A STATUS WORD BEING CHANGED D M YES UNIT 24 FOR STORAGE.

DOES THE SECOND OR SINGLE NO I OPERAND ADDRESS HAVE A MODE-O OPERAND ADDRESS YES TRKNSF EFT TT-IE STATU S WOR I) T0 THE MEMORY TRANSFER THE DATA FROM THE ADDRESS UNIT 46 TO THE REGISTER IN THE REGISTER MEMORY 4O DESIGNATED BY THE OPERAND ADDRESS.

TERM

FIG.6E

INVENTORS HAROLD L. McFARLAND BY JAMES F O'LOUGHLIN ado-u 01.06 a; [41m ATTORNEYS IS THE DECODED INSTRUCTION YES A HALT" INSTRUCTION T STORE THE CONTENTS OF THE RO REGISTER IN THE REGISTER MEMORY 40 IN THE B INPUT CIRCUIT 52 FOR CONSOLE DISPLAY ISR-0 STOP I Q HAS A PERIPHERAL UNIT BEEN N0 SELECTED FOR BUS CONTROL? YES I ISR'I sToRE PC REGISTER AND STATUS REGISTER T CONTENTS AND LOAD NEw PROGRAM COUNT AND R sTATus woRD INTO THE PC AND STATUS REsIsTERs FETCH INvENToRs HAROLD L. MCFARLAND BYJAMES F. O'LOUGHLIN G302?" (7115x6 4); ATTO R NE YS PATENTEDncr 19 Ian SHEEI 13I1F 21 OPERATING PROGRAM INTERRUPTION INSTR T ROUTINE INSTRUCTIONS MEMORY UNIT FIG. IO

SELECTED INPUT CIRCUIT FIRST OPERAND SECOND OR SINGLE OPERAND ADDRESS ADDRESS MODE #0 MODE=0 ADDRESS INSTRUCTION ADDRESS ADDRESS ADDRESS MODE=D MQDEiQI MOV ADD

SUB

CMP

BIT

BIC

BIS

TST

COM

INC or ADC DEC or SBC CLR NEG

FIG 8 INVENTORS HAROLD McFARLAND JAMES F. O'LOUGHLIN AT TORNE YS PATENTEDGDT 19I97| 3,614,741

SHEET 1W 21 IITILILJIFLFI READ/WRITE CYCLES D{I\Z3QIIZI3IQI}Z3,Q

WRITE l I L m.

SHIFT REGISTER I A 2 3 4 STATE -+|SR-B TIMING uNIT 66 INSTRucTIoN 76 a SHIFT REGISTER I TIMING iIGNAL 1 R T TIMING CLOCK GENE OR 5 CIRCUIT (CLK) SW7 FIG 78 CLET' II RE CONTROL UNIT $60 -'-BSR-fl BSR-I BUS SHIFT HAROLD L. McFARLAND S'GNAL GENERATOR JAMES F. O'LOUGHLIN I l REGISTER l INVENTORS I I BY B5 R '7 32 I! I44); Arum? AT TURN EYS PATENTEDUCT 19 l9?! SHEEI lSUF 21 ll |l lllllillulll lllllllll QEE 5604 ti u T5 'llllllnllllllnllll I'lllllllllllll-lllllllllll-I. I'll-III- ISR-0 AND -I TRANSFER "Mov PCIZLRGISI" To INSTRUCTION DECODER 64-, INCREMENT THE CONTENTS OF THE PC REGISTER; DECODE THE INSTRUCTION TRANSFER THE PC REGISTER coNTENT"To' THE sus ADDREss REGISTER 34-, RETRIEVE THE NExT LOCATION coNTENTs As DATA;

ISR'I INCREMENT THE B CIRCUIT INPUT CONTENTS AND TRANSFER THE ADDER UNIT OUTPUT TO THE PC REGISTER; TRANSFER THE DATA To THE 8 INPUT CIRCUIT 52 (ISR-2:3)

, TRANSFER THE DATA FROM THE 8 INPUT CIRCUIT 52 TO THE SOURCE REGISTER TRANSFER DECREMENTED R6 REGISTER ISR CONTENTS TO THE BUS ADDRESS REGISTER 34 AND TRANSFER THE ADDRESSED CONTENTS TO THE 5 INPUT CIRCUIT 52 TRANSFER THE coNTENTs OF THE 5 INPUT CIRCUIT 52 TO THE BUS ADDREss REGISTER ISR 2 AS A DATA ADDRESS AND TRANSFER DATA TO THE 8 INPUT CIRCUIT 52 |sR TRANSFER THE CONTENTS OF THE SOURCE REGISTER TO THE B INPUT CIRCUIT 52 TRANSFER THE DATA THROUGH THE ADDER SR UNIT ONTO THE BUS 30 FOR STORAGE IN THE ADDRESS IDENTIFIED BY THE CONTENTS OF THE BUS ADDRESS REGISTER 34 HAROLD L. III-FEAT 34 0 JAMES F. O'LOUGHLIN BY ATTORNEYS PATENIEDUET I 9 IHTI IRS-0, AND -I IRS -I IRS 2 IRS IRS-0 IRS-I IRS -4 SIIEEI 18IIF 21 TRANSFER "ADD R2I6), RQIQY'TO THE INSTRUCTION DECODER 64; INcREMENT THE CONTENTS THE PC REGISTER; DECODE THE INSTRUCTION TRANSFER THE CONTENTS OF THE PC REGISTER TO THE BUS ADDRESS REGISTER 34; INCREMENT THE PC REGISTER CONTENTS; TRANSFER THE INDEX VALUE TO THE B INPUT CIRCUIT 52 TRANSFER THE R2 REGISTER CONTENTS TO THE A INPUT CIRCUIT; TRANSFER THE OUTPUT FROM THE ADDER UNIT 46 TO THE BUS ADDRESS REGISTER 34-, TRANSFER THE CONTENTS OF THE ADDRESSED LOCATION TO THE B INPUT CIRCUIT 52 TRANSFER THE CONTENTS OF THE 8 INPUT CIRCUIT 52 TO THE SOURCE REGISTER TRANSFER THE CONTENTS OF THE R0 REGISTER TO THE B INPUT CIRCUIT 52 TRANSFER THE CONTENTS OF THE SOURCE REGISTER TO THE A INPUT CIRCUIT 48 TRANSFER THE SUM FROM THE ADDER UNIT 46 TO THE R0 REGISTER FIG. I4

INVENTORS HAROLD L. MCFARLAND JAMES E O'LOUGHLIN ATTORNEYS PATENTEDIIET 19 Ian ISR D AND I ISR '0 ISR'I ISR '0 SIIEEI 19 [1F 21 TRANSFER "sue R4I4). RID(|I"TO THE INSTRUCTION DECODER s4; INCREMENT THE CONTENTS OF THE PC REGISTER;

DECODE THE INSTRUCTION I M ME TRANSFER THE B INPUT CIRCUIT 52 To THE SOURCE REGISTER TRANSFER THE CONTENTS OF THE R0 REGISTER TO THE B INPUT CIRCUIT 52; TRANSFER THE OUTPUT OF THE ADDER UNIT 46 TO THE BUS ADDRESS REGISTER 34 AND THE CONTENTS OF THE ADDRESSED LOCATION TO THE B INPUT CIRCUIT 52 EXECUTE TRANSFER souRcE REGISTER CONTENTS, To THE A INPUT CIRCUIT 46 AND MODIFY.

TRANSFER THE DATA FROM THE ADDER UNIT 46 ONTO THE BUS 30 FOR STORAGE IN THE ADDRESS IDENTIFIED BY THE CONTENTS OF THE BUS ADDRESS REGISTER 34 INVENTORS HAROLD L. McFARLAND JAMES F. O'LOUGHLIN ATTORNEYS FIG. I5 

1. A data processing system including a plurality of addressed locations in a processor unit for processing information stored at addressed locations in response to instructions with address portions, said processor unit comprising: A. a plurality of addressed storage registers constituting additional addressed locations, each of said instructions having an address portion defining only one of said registers, and one of said registers being a program counter for controlling the processor unit, B. a transfer unit coupled to the address locations, and C. a control unit including:
 1. a register selector responsive to one of the instructions for selecting the register addressed by the instruction address portion, and
 2. a transfer control unit responsive to said register selector for connecting said transfer unit to said selected register to convey information to or from said selected register.
 2. a transfer control unit responsive to said register selector for connecting said transfer unit to said selected register to convey information to or from said selected register.
 2. A data processing system as recited in claim 1 wherein each instruction address portion defines an address mode and a register address, said register selector being responsive to the register address for selecting said register and said control unit additionally comprising an address mode controller responsive to the address mode for modifying the utilization of the selected register contents by said processor unit.
 2. a timing unit responsive to the timing control signal for causing said decoder to generate first and second address signals sequentially,
 2. an instruction decoder responsive to instructions for identifying those instructions with address mode and register selection portions,
 3. a register selector responsive to said instruction decoder and an instruction register address portion for selecting any of said registers,
 3. a register selector responsive to said timing unit and said instruction decoder for selecting the registers addressed by said instruction address portion as first and second of said addressed registers in sequence, and
 3. A data processing system as recited in claim 2 for responding to a first instruction address mode, said address mode controller and said transfer control unit being responsive to the first address mode for connecting said transfer unit to said selected register for conveying the selected register contents as the information.
 4. A data processing system as recited in claim 2 for responding to a second instruction address mode wherein: A. said address mode controller and said transfer control unit are responsive to the second address mode for connecting said transfer unit to a second location defined by the selected register contents for conveying the information to or from the second location, and B. said transfer unit includes means responsive to said address mode controller for incrementing the selected register contents.
 4. a transfer control unit responsive to said register selector for connecting said transfer unit to said selected registers in sequence to convey information.
 4. A transfer unit including gating means and an arithmetic unit responsive to said instruction decoder for modifying data in accordance with the instruction, said gating means coupling said transfer unit to an addressed location,
 5. an address mode controller responsive to said instruction decoder and the address mode portion, and
 5. A data processing system as recited in claim 2 for responding to a third instruction address mode wherein: A. said transfer unit includes means responsive to said address mode controller and said register selector for immediately decrementing the selected register contents, and B. said address mode controller and said transfer control unit are responsive to the third address mode for connecting said transfer unit to a second location defined by the decremented selected register contents for conveying the information to or from the second location.
 6. A data processing system as recited in claim 2 for responding to a fourth instruction address mode and related index value wherein: A said transfer unit includes an adder unit, B. said address mode controller, said register selector unit and said transfer control unit are responsive to the fourth address mode for adding the selected register contents and index value to obtain an adder unit output, and c. said address mode controller and said transfer control unit Are responsive to the fourth address mode for connecting said transfer unit to a second location defined by the adder unit output for conveying the information to or from the second location.
 6. a transfer control unit responsive to said address mode controller and said register selector for enabling said transfer unit to transfer data to or from said selected register.
 7. A data processing system as recited in claim 2 wherein the instruction address portion indicates first and second deferral states and wherein said address mode controller and said transfer control unit respond to the first deferral state for connecting said transfer unit to the selected location, said address mode controller and transfer control unit connecting said transfer unit to a second location defined by the selected location contents to convey the information to or from the second location in response to a second deferral state.
 8. A data processing system as recited in claim 7 for responding to an instruction with a first address mode and second deferral state, said address mode controller and said transfer control unit being responsive to the instruction for connecting said transfer unit to the second location defined by the selected register contents to convey the information with the second location.
 9. A data processing system as recited in claim 7 for responding to an instruction with a second address mode and second deferral state wherein: A. said address mode controller and said transfer control unit are responsive to the instruction for connecting said transfer unit to the second location defined by the contents of a third location addressed by the selected register contents to convey the information to or from the second location, and B. said transfer unit includes means responsive to said address mode controller for incrementing the selected register contents.
 10. A data processing system as recited in claim 7 for responding to an instruction with a third address mode and a second deferral state wherein: A. said transfer unit includes means responsive to said address mode controller and said register selector for immediately decrementing the selected register contents, and B. said address mode controller and said transfer control unit are responsive to the instruction for connecting said transfer unit to the second location defined by the contents of a third location addressed by the decremented register contents for conveying the information to or from the second location.
 11. A data processing system as recited in claim 7 for responding to an instruction with a fourth address mode and a second deferral state and a related index value wherein: A. said transfer unit includes an adder unit, B. said address mode controller, said register selector and said transfer control unit are responsive to the fourth address mode for adding the selected register contents and the index value to obtain an adder unit output, and C. said address mode controlled and said transfer control unit are responsive to the fourth address mode and second deferral state for connecting said transfer unit to the second location defined by the contents of a third location addressed by the adder unit output for conveying the information to or from the second location.
 12. In a data processing system including a plurality of addressed locations and a processor unit for processing information stored at addressed locations in response to instructions with first and second address portions, said processor unit comprising: A. a plurality of addressed registers constituting additional addressed locations, each instruction address portion defining only one of said registers and one of said registers being a program counter for controlling the processor unit, B. a transfer unit coupled to the addressed locations for selectively conveying information to or from first and second of the addressed locations, and C. a control unit including:
 13. A data processing system as recited in claim 12 wherein each instruction address portion includes an address mode portion and a register address, said register selector being responsive to the first and second address signals for selecting said addressed registers in sequence and said control unit additionally comprising an address mode controller responsive to the address mode for modifying the utilization of the selected register contents by said processor unit.
 14. A data processing system as recited in claim 13 for responding to a first address mode in one instruction address portion, said address mode controller and said transfer control unit being responsive to the first address mode and said timing unit for connecting said transfer unit to the selected register for conveying the information to or from said selected register.
 15. A digital computer as recited in claim 13 for responding to a second address mode in one address portion of an instruction wherein: A. said address mode controller and said transfer control unit are responsive to the second address mode and said timing unit for connecting said transfer unit to an addressed location defined by the selected register contents for conveying the information contained therein, and B. said transfer unit includes means responsive to said address mode controller for incrementing the selected register contents.
 16. A digital computer as recited in claim 15 wherein the one address portion identifies said program counter as said selected register, said control unit connecting said transfer unit to the addressed location following the instruction to convey the information.
 17. A data processing system as recited in claim 13 for responding to a third address mode in one address portion of an instruction, wherein: A. said transfer unit includes means responsive to said address mode controller, said register selector and said timing unit for decrementing the selected register contents and B. said address mode controller and said transfer control unit are responsive to the third address mode and said timing unit for connecting said transfer unit to a second location defined by the decremented selected register contents for conveying information to ro from the second location.
 18. A data processing system as recited in claim 13 for responding to a fourth address mode in one address portion of an instruction and a related index value wherein: A. said transfer unit includes an adder unit, B. said address mode controller, said register selector and said transfer control unit are responsive to the fourth address mode and said timing unit for adding the selected register contents and index value to obtain an adder unit output, and C. said address mode controller and said transfer control unit are responsive to the fourth address mode and said timing unit for connecting said transfer unit to a second location defined by the adder unit output for conveying the information to or from the second location.
 19. A data processing system as recited in claim 18 wherein the one address portion identifies said program counter as said selected register, said control unit connecting said transfer unit to said program counter for adding the program counter contents and index value to obtain the address for the second location.
 20. A data processing system as recited in claim 13 wherein each instruction address portion indicates first and second deferral states and wherein said address mode controller and said transfer control unit respond to said timing unit and the first deferral state for connecting said transfer unit to the selected location, said address mode controller and said transfer control unit connecting said transfer unit to a second location defined by the selected location contents to convey the information to or from the second location during the second deferral state.
 21. A data processing system as recited in claim 20 wherein each address portion in an instruction comprises diverse address modes and register addresses, said transfer control unit being responsive to said address mode controller, said register selector, said timing unit and said instruction decoder for connecting said transfer unit to a first location defined by one address portion for conveying information to said processor unit and to another location as defined by the other address portion for transferring information from said processor unit to the second location.
 22. A data processing system comprising A a plurality of addressed locations including a memory unit for storing operating instructions in sequence, certain instructions including at least one operand address consisting of address mode and register address portions, and B. a processor unit including:
 23. A data processing system as recited in claim 22 wherein said address mode controller and said transfer control unit respond to second contents of the address mode portion for connecting said transfer unit to a second location addressed by the selected register contents for conveying data.
 24. A data processing system as recited in claim 23 wherein said address mode controller and said transfer control unit respond to third contents of the address mode portion for connecting said transfer unit to the second location, the second location being addressed by the contents of a third location addressed by the selected register contents to convey data to or from the second location. 